#JR1968190
up IP performance monitor and report the performance status
What We Need To See:
Be proficient in Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
Track record of first-pass success in ASIC Development
B.S. or M.S. degree in Computer Engineering or Electrical Engineering
1+ years of experience owning processing ASIC, IP or SoC design verification
Experience in delivering mixed language UVM and C++ testbenches
Ability to interpret functional specs and creating test plans
Ability to write directed and constraint random test to achieve coverage-driven verification closure
Experience developing tools and infrastructure using Perl or Python
Ways to stand out from the crowd: