Senior Custom SOC IP Verification Engineer

on, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution

• Partner with internal and external cross-functional teams, individual contributors and peers including customers

• Contribute to and drive development of silicon and platform verification strategy and methodology

• Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing

• Identify candidates, hire, schedule, support and train a team of verification engineers to develop products on time and on budget and with first-time right results

• Contribute to, analyze, review supporting SOC and IP architecture and technical documentation, requirements and develop high quality verification plans, negotiate feedback to meet the needs of the program and customers

• Support engineering teams to define, debug, implement and deliver total solutions around purpose-built ASICs

• Define, implement and maintain key performance indicators (KPI) for areas of responsibility

• Partner with technical program management and supply chain team members to manage internal and external development partners and vendors

What we need to see:

• Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
• Track record of first-pass success in ASIC Development
• B.S. or M.S. degree in Computer Engineering or Electrical Engineering
• Experience working across multiple projects and adjusting priorities in partnership with stakeholders
• 8+ years of experience owning processing ASIC, IP or SoC design verification
• Experience managing and delivering complex mixed language UVM and C++ testbenches
• Ability to interpret functional specs and creating comprehensive test plans
• Ability to write directed and constraint random test to achieve coverage-driven verification closure
• Experience developing tools and infrastructure using Perl or Python
• Hands-on experience with AMBA protocols such as AXI, ACE, CHI, ATB, etc.
• Hands-on experience with complex subsystems in new technologies like ARM CPU complex, LPDDR, HBM, GPU's, DLA, PCIE or Network on chip and with performance verification