#R45608
Tech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design verification engineer, with a large portion of the recent work experience on RTL integration and verification.
6-10 years of core RTL integration and verification experience using Verilog is a must.
System Verilog experience and experience with UVM based environment usage / debugging is required.
PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is a must.
Prior experience in IP development teams would be an added advantage.
Scripting knowledge is an advantage.
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