Lead Design Engineer - Verification

Cadence Design Systems

4.4

Shanghai, China

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Flexible work options available

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#R51945

ce preferred.

Develop and execute verification plans for SOC and IP blocks, ensuring design intent and testability.
Perform RTL verification using industry-standard methodologies (e.g., UVM, SystemVerilog).
Collaborate with design engineers to address complex debug issues and optimize verification strategies.
Work closely with customer and internal engineering teams to deliver high-quality support and service.
Participate in coverage analysis, regression testing, and closure of verification goals.
Contribute to the development and enhancement of verification environments and reusable testbenches.

Requirements:

Bachelor's or Master's degree in Electrical/Computer Engineering or related field with 3-5 years of experience in VLSI/SOC design verification.
Strong expertise in System Verilog, UVM, and Verification tools.

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