Principal Design Engineer

Cadence Design Systems

4.4

Bengaluru, India

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Parental leave is available for both paternity and maternity

Flexible work options available

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, and east coast) teams, which work in different time-zones.

Primary Responsibilities:
- Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
- Support DDR Controller and PHY SOC integration reviews, and integration questions.
- Perform RTL and gate level simulations to verify functionality.
- Assist customers with gate level simulations and timing closure.
- Participate in development of CDNS documentations and checklists for customers.
- Support post silicon bring-up and deployment activities by our customers.
- Enhance customer experience by providing prompt updates to customers.

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