#R44711
r scripting languages is a plus.
• Experience in post silicon validation, ATE debug and support is desired.
• Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.
• Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.
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