ASIC Physical Design Intern

ption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD intern at NVIDIA, you'll learn and work on the tasks from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work.

What you'll be doing:

• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan

• Synthesis, RTL/netlist quality check, formal verification, function eco creation

• Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc.

• Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue

• Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas

• Methodology in any of above areas.

What we need to see:

• Currently pursuing a Master's or PhD degree within a relevant or related field

• Strong knowledge in IC design

• Passionate about technology research and IC backend

• Self-driven, good leaning ability, good teamwork

• Excellent communication skill, proficient in English reading and writing

Ways to stand out from the crowd:

• Experience in IC backend implementation

• Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC)

• Proficient user of Python or TCL

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!