Formal Verification Engineer - New College Graduate

lement testplans using innovative formal techniques.

• Drive tools to realize their best performance.

• Develop flow and script to automate and improve team efficiency.

• Collaborate with other teams to help produce bug free, outstanding silicon products.

What we need to see:

• BS/MS/Ph.D. or equivalent experience in CS/CE/EE/Mathematics

• Strong analytical and collaboration skills to solve complex problems.

• Strong coding skills in C, Perl, Python or any other industry-standard scripting languages

• Good debugging skills

• Excellent communication skills, able to effectively collaborate and work with members of a distributed team.

Ways to stand out from the crowd:

• Knowledge of formal verification methodologies, techniques and tools like Jasper.

• Hands-on experience with Verilog / System Verilog HDLs, SVA assertions, and able to understand complex RTL code quickly.

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most dedicated and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you!

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.