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Cadence Design Systems

Lead Design Engineer

Aug 9, 2026• Hyderabad, India

About us

Cadence is a pivotal leader in computational software.

★ 4.4 out of 5 · 53 reviews

  • Size: 10,000+ employees
  • Industry: Technology: Manufacturing
View company profile ›

Why you should apply for a job to Cadence Design Systems:

  • Ranked as one of the Best Technology Companies in 2024
  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Development, automation and maintenance of EDA flows and scripts for physical implementation
  • Develop TFM to optimize PPA for IP's and Soft Controllers
  • PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
  • Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
  • Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
  • Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
  • Required skills -
  • Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years' experience
  • Physical design experience in ASIC design environment
  • Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
  • Should have excellent leadership, communication, analytical and problem solving skills.
  • Expertise on High frequency design methodologies for complete ASIC backend flows.
  • Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
  • Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
  • Solid scripting skills including Python and Tcl.
  • Should be self-motivated and good team player.

We're doing work that matters. Help us solve what others can't.

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Additional Information

  • Posted: Aug 9, 2026
Apply on company site
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