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Cadence Design Systems

Lead Design Engineer

Jun 18, 2026• Pune, India

About us

Cadence is a pivotal leader in computational software.

★ 4.4 out of 5 · 53 reviews

  • Size: 10,000+ employees
  • Industry: Technology: Manufacturing
View company profile ›

Why you should apply for a job to Cadence Design Systems:

  • Ranked as one of the Best Technology Companies in 2024
  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities:

  • The Candidate will have design responsibility, including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power / EM-IR signoff, physical verification (DRC/LVS/Antenna), and DFM Closure.
  • Physical design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools
  • Physical design for PPA optimization of performance and power-oriented best-in-class interface IPs such as DDR, LPDDR, PCIE, UCIE, etc and test chips for advanced process nodes, such as 7nm/5nm/3nm/2nm
  • An opportunity to work on many varieties of challenging designs, i.e., low power, high-speed and area optimized designs.
  • Work closely with RTL design team & Analog Team to ensure on-time, successful tapeouts.

Required skills -

  • B.Tech/BE/ME/Mtech with 4-6 years hands-on experience in physical design and physical verification.
  • Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
  • Solid knowledge on physical design, static timing analysis, Low Power Design, EM/IR /crosstalk analysis, formal verification, physical verification, DFM, DFT.
  • Successful track records of taping out complex IP's & SoC's at 16/10/7/5/3 nm with different foundries.
  • Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus will be an added advantage
  • Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/python assisted with AI.
  • Should have excellent communication, analytical and problem-solving skills, should be self-motivated and good team player

We're doing work that matters. Help us solve what others can't.

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Additional Information

  • Posted: Jun 18, 2026
Apply on company site
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