Principal Design Engineer - Physical Design
Oct 6, 2026 Shanghai, China
About us
Cadence is a pivotal leader in computational software.
- Size: 10,000+ employees
- Industry: Technology: Manufacturing
Why you should apply for a job to Cadence Design Systems:
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
About the team:
Our team deliver many high-performance products based on the industry's most advanced technology with high frequencies up to 8800MHz.Our product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Job Responsibilities:
Focus on high-speed digital DDR PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
Job Requirement:
-BS with minimum 7+ years of experience. MS with minimum 5+ years of experience.
-Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.
We're doing work that matters. Help us solve what others can't.
Job Description
About the team:
Our team deliver many high-performance products based on the industry's most advanced technology with high frequencies up to 8800MHz.Our product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Job Responsibilities:
Focus on high-speed digital DDR PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
Job Requirement:
-BS with minimum 7+ years of experience. MS with minimum 5+ years of experience.
-Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.
We're doing work that matters. Help us solve what others can't.
Additional Information
- Posted: Oct 6, 2026