88 jobs for "SoC Physical Design Methodology Engineer"

SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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CPU Physical Design Methodology and Optimization Engineer

At Apple - Santa Clara

Posted on Oct 7

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CPU Physical Design Methodology and Optimization Engineer

At Apple - Santa Clara

Posted on Oct 7

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Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 27

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Lead Product Engineer - Genus & Innovus

At Cadence Design Systems - Shanghai

Posted on Jul 23

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SoC FE Implementation Engineer

At Apple - Cupertino

Posted on Oct 19

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Physical Design Signoff Engineer

At Apple - Austin

Posted on Oct 19

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SoC Power Analysis and Optimization Engineer

At Apple - Austin

Posted on Oct 17

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Timing Design Engineer

At Apple - Cupertino

Posted on Oct 16

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IC Package Design Engineer

At Apple - Austin Metro Area

Posted on Oct 15

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Timing Design Engineer

At Apple - Austin

Posted on Oct 14

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Timing Design Engineer

At Apple - San Diego

Posted on Oct 14

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Timing Design Engineer

At Apple - Beaverton

Posted on Oct 8

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Timing Design Engineer

At Apple - Waltham

Posted on Oct 8

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SoC Power Analysis and Optimization Engineer

At Apple - Austin

Posted on Oct 17

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SoC Power Analysis and Optimization Engineer

At Apple - Austin

Posted on Oct 17

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SoC Power Analysis and Optimization Engineer

At Apple - Austin

Posted on Oct 17

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CPU Clock Implementation Engineer

At Apple - Santa Clara

Posted on Oct 17

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Cadence Design Systems

Lead Product Engineer - Genus & Innovus

Shanghai, ChinaPosted Jul 23, 2026

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities - Foundry Design Service Team Support

Develop and maintain Genus-to-Innovus digital implementation reference flows for foundry design service teams.
Support RTL synthesis, floorplanning, placement, CTS, routing, and physical optimization for production SoC designs.
Provide methodology guidance on timing closure, congestion mitigation, and power-aware implementation at advanced nodes.
Support hierarchical and block-based implementation flows used in design services and multi-project environments.
Diagnose and resolve convergence issues impacting timing, power, area, and routability in late design stages.
Enable reusable, standardized implementation flows across multiple foundry design service programs.

Foundry Common Requirements - Genus & Innovus Enablement

Support foundry-preferred synthesis and place-and-route methodologies aligned with signoff expectations.
Enable consistent constraint handling (SDC, UPF) across RTL synthesis and physical implementation stages.
Support power-intent driven implementation flows including low-power optimization and power domain integration.
Provide guidance on advanced-node challenges such as routing congestion, multi-patterning-aware placement, and CTS robustness.
Support integration of Genus and Innovus flows with signoff tools such as Tempus, Quantus, Voltus, and Pegasus.
Assist design service teams with ECO implementation, late-stage timing closure, and tapeout readiness.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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