58 jobs for "SerDes Circuit Design Engineer"

IP Engineer

At Apple - San Francisco Bay Area

Posted on Oct 16

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CMOS SerDes or High-speed I/O, Lead Analog IC Design Engineer

At Cadence Design Systems - San Jose

Posted on Sep 30

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Analog Layout Automation Engineer (f/m/d)

At Apple - München

Posted on Oct 7

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Principal Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Sep 29

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Sr Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Sep 16

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Analog Layout Automation Engineer

At Apple - Haifa

Posted on Oct 16

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Lead Analog Layout Design Engineer (SerDes)

At Cadence Design Systems - Cork

Posted on Aug 28

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Lead Analog Layout Design Engineer

At Cadence Design Systems - Cork

Posted on Aug 20

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Principal Design Engineer

At Cadence Design Systems - Cork

Posted on Aug 13

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Design Engineer

At Cadence Design Systems - Shanghai

Posted on Jul 21

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jun 8

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IP Engineer

At Apple - San Francisco Bay Area

Posted on Oct 16

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jun 8

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IP Engineer

At Apple - San Francisco Bay Area

Posted on Oct 15

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jun 4

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IP Engineer

At Apple - San Francisco Bay Area

Posted on Oct 15

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Design Engineering Architect

At Cadence Design Systems - Bangalore

Posted on Jun 4

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PLL Design Engineer

At Apple - Austin

Posted on Oct 19

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Analog Mixed-Signal Modeling Software Engineer

At Apple - Cupertino

Posted on Oct 17

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Analog Mixed-Signal Design Software Engineer

At Apple - Cupertino

Posted on Oct 15

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Cadence Design Systems

Principal Design Engineer

Bangalore, IndiaPosted Jun 8, 2026

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.

Job Responsibilities:

Design of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)

Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications

Work closely with Layout Design Engineers to design IC circuit blocks and PMA sections

Work with Technical Team Leads in the areas of circuit design and SERDES architectures

Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications:

BEng, MEng, PhD or equivalent.

Candidate's background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design

Should have a good understanding of jitter and signal equalization techniques

Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators

Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment

Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification

Additional Skills/Preferences:

Cadence tool experience is desirable and design experience at >10Gbps and in < 16nm technologies

Lab test experience as part of silicon evaluation is advantageous

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About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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