18 jobs for "CPU Debug and Power Management Verification Engineer"

Apple's wireless chip powers connectivity across every new iPhone - and its successor is already taking shape. Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization owns every aspect of wireless silicon development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. It is driven by a world-class, vertically integrated team spanning RF/Analog, Systems/PHY/MAC, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a Wireless SOC Design Verification Engineer, you'll be at the heart of the chip design effort - owning a meaningful verification scope and growing it project to project.

Description

You'll be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff. Working closely with architects, designers, and firmware engineers, you'll build reusable testbenches and verification environments using modern, metric-driven methodology. Areas you may work on include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY Verification, Radio integration, and peripherals such as SPI - choosing simulation, formal, or whichever approach the design actually calls for. Low power is part of your scope wherever it shows up: you'll verify power intent using UPF within your area.

Over time, you can grow deeper into the IPs and subsystems you know best, or broader - across IPs and up from block level to full SOC integration. The team is also pushing hard on AI-assisted verification, and you'll help figure out where it fits best: test generation, debug, coverage closure, or all the above.","responsibilities":"Partner with architects and designers early to build detailed verification plans from specifications - before RTL lands, not after.

Develop reusable block/IP and subsystem-level UVM testbenches, and support IP integration into the SOC.

Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.

Debug failures, including corner cases, and manage bug tracking through resolution.

Verify low-power design intent using UPF within your scope.

Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level up through top-level SOC integration.

Apply formal verification where it fits - the team will help you ramp up.

Build and improve automated regression flows and contribute to methodology in your area.

Explore and apply AI-assisted verification techniques to improve team productivity.

Participate in verification reviews and uphold high coding-quality standards.

Support post-silicon bring-up as needed.

Preferred Qualifications

Experience taking at least one ASIC/SOC from concept through tape-out.

Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.

Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.

Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction.

Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold).

Experience defining coverage space and writing coverage models.

Experience with embedded CPU verification; programming in C/C++ or assembly.

Scripting in Python or Perl; interest in applying AI/ML to verification workflows

Great teammate with excellent communication skills and the desire to take on diverse challenges.

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience.

Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.

Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.

Solid problem-solving and debugging skills with constrained-random verification.

Understanding of digital logic design, SOC architecture, and microarchitecture.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

About Apple

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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