9 jobs for "Digital Electronics Principal Verification Engineer"

Digital Electronics Principal Verification Engineer

At Cadence Design Systems - Edinburgh

Posted on Oct 22

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Senior Principal Design Engineer

At Cadence Design Systems - Nanjing

Posted on Oct 12

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Principal Design Engineer - Physical Design

At Cadence Design Systems - Shanghai

Posted on Oct 6

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Principal Design Engineer

At Cadence Design Systems - Austin

Posted on Oct 1

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Principal Product Engineer - DIP

At Cadence Design Systems - Shanghai

Posted on Aug 7

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Sr Principal Product Validation Engineer

At Cadence Design Systems - Noida

Posted on Feb 23

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Principal Design Engineer

At Cadence Design Systems - Austin

Posted on Oct 1

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jun 23

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Principal Product Validation Engineer

At Cadence Design Systems - Noida

Posted on Jan 20

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Cadence Design Systems

Principal Design Engineer - Physical Design

Shanghai, ChinaPosted Oct 6, 2026

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
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89% would recommend this company to other women
87% say the CEO supports gender diversity

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

About the team:

Our team deliver many high-performance products based on the industry's most advanced technology with high frequencies up to 8800MHz.Our product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.

Job Responsibilities:

Focus on high-speed digital DDR PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.

Job Requirement:

-BS with minimum 7+ years of experience. MS with minimum 5+ years of experience.

-Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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