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Cadence Design Systems

Digital Electronics Principal Verification Engineer

Edinburgh, United KingdomPosted 16 days ago

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Digital Electronics Principal Verification Engineer

Location: Edinburgh

Reports to: Design Engineering Group Director

Job Overview:

The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume.

The Cadence SSG Vision is to deliver industry leading IP and Chiplet solutions to enable our customers to be successful across these fast-moving application spaces.

The Digital Principal Verification Engineer will be based in Edinburgh, Scotland as part of an experienced Chiplet Team with long established research and development sites in Europe and India.

Job Responsibilities:

Development of Verification and Emulation Environments for complex Chiplet Designs

Development of UVM-SV Scoreboards for self-checking regressions

Development of Functional Coverage as part of Metric Driven Verification Environments

Development of SystemVerilog Assertions for use in Formal and Simulation Environments

Development of Emulation Environments based on Cadences Palladium Emulator Product

Integration of Cadence Verification IP (VIP) for Simulation Environments

Integration of Accelerated VIP (AVIP) for Emulation Environments

Definition and Management of Verification Plans (vPlans) using Cadence vManager tools

Creation and Management of Automated Regression Environments, e.g. Jenkins, GIT

Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001

Close Collaboration with Architects and Design Engineers to debug complex test scenarios

Job Qualifications:

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline

10+ years' experience in microelectronics/EDA industry

Experience of Verilog RTL Design essential

Experience of Metric Driven Verification (MDV) essential

Experience of Formal Verification Methodologies essential

Excellent oral and written English essential

Self-motivated with excellent planning, interpersonal, and communication skills

Additional Skills/Preferences:

Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred

Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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