8 jobs for "CAD Engineer - EMIR Signoff"

Physical Design Signoff Engineer

At Apple - Austin

Posted on Oct 19

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SoC Physical Design Engineer, PnR

At Apple - San Diego

Posted on Oct 19

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SoC Physical Design Engineer, PnR

At Apple - Waltham

Posted on Oct 17

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CPU Full-chip Physical Integration Engineer

At Apple - Beaverton

Posted on Oct 16

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CPU Full Chip Physical Integration Engineer

At Apple - Austin

Posted on Oct 10

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SoC Physical Design Engineer, PnR

At Apple - San Jose

Posted on Oct 17

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SoC Physical Design Engineer, PnR

At Apple - San Jose

Posted on Oct 14

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CPU Full Chip Physical Integration Engineer

At Apple - Austin

Posted on Oct 9

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Apple

Physical Design Signoff Engineer

Austin, TXPosted 19 days ago

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We're seeking a Physical Design Signoff Engineer to join our team and drive the final verification stage of SOC design across Apple's Hardware Tech group. Signoff is the critical last checkpoint before tapeout, where designs are validated against manufacturing, timing, and power criteria. In this role, you'll own signoff closure for blocks and full-chip designs, working closely with design and CAD teams to make sure silicon is ready for production.

Description

The Physical Design Signoff Engineer will define and own the signoff criteria for PD/PNR designs across static timing analysis, signal integrity, EMIR, and clock construction and simulation, and will drive signoff reviews with design teams through readiness assessment, closure of open items, and alignment of methodology across groups. We are looking for a rigorous, self-driven engineer with deep physical design expertise, a team player who pays a high level of attention to detail, communicates clearly with designers under tape-out pressure, and is equally comfortable debugging a timing or IR drop violation and setting the bar that determines when a block is done. The role requires developing and maintaining the signoff checks, scripts, automation, and dashboards used for verification and metric tracking, enabling and supporting design teams on that signoff infrastructure, and performing flow signoff to verify that CAD flows are generating correct results. You'll partner cross-functionally with PNR design, CAD, Technology, and Power teams to keep methodology consistent and grounded in what the technology and tools can deliver.

Preferred Qualifications

Proficient in programming using Python, Perl or Tcl

Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, or Tempus

Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon

Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction

Excellent communication skills and ability to collaborate across design, CAD, and technology teams

Understanding of tradeoffs to meet PPA (power, performance, area) targets, and experience defining implementation recipes to improve PPA

Minimum Qualifications

BS in Computer Science or related field with 10+ years of relevant industry experience

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Industry: Technology: Manufacturing

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