3 jobs for "Chip Lead / Physical Design Director"

DFT Engineer (M, F, D)

At Apple - Munich

Posted on Oct 17

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 15

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DFT Engineer (M, F, D)

At Apple - München

Posted on Oct 12

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Apple

DFT Engineer (M, F, D)

Munich, GermanyPosted 22 days ago

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Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, inquisitive people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our multifaceted group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Are you ready to join a team redefining hardware technology? We are searching for a passionate engineer to join our exciting team of problem solvers.

Join us!

Description
As a DFT engineer, you will lead the complete DFT solution for a chip project, with responsibilities spanning all aspects of semiconductor development.","responsibilities":"You will create DFT specifications, create verification plans, and define the SoC test interface.
You will develop and implement the DFT architecture and own its integration into large SoC blocks - including IP integration, system and control bus connectivity, and the integration of memories and hard macros.
You will implement testbenches, generate directed and constrained-random tests, debug failures, run gate-level simulations, and close coverage.
You will also generate structural test vectors, run synthesis and timing closure and work closely with Chip Architecture, DV, Physical Design, and Power teams to achieve first-tapeout success.
Additional responsibilities include supporting STA, physical, power, and logical analysis for DFT modes, partnering with Test Engineers to bring up test vectors on silicon.

Preferred Qualifications
Experience developing DFT specifications and driving DFT architecture and methods for designs
Proven Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
Experience debugging compressed ATPG patterns, MBIST, and JTAG/1500 related issues.
Experience with STA constraints development and analysis for DFT modes, as well as SDF simulations.
Ability to conduct experiments during silicon debug, gathering and analyzing data, and using scripting to support efficient handling of ATE data.
Excellent problem-solving and communication skills.
Experience in large SoC design or verification.

Minimum Qualifications
B.Sc./M.Sc./PhD in Electrical Engineering, Computer Science, or a related field.
Solid knowledge of industry-standard DFT practices, including ATPG, JTAG, MBIST, and the trade-offs between test quality and test time.
Proficient in Verilog and/or VHDL, with hands-on experience using simulators and waveform debugging tools.
Experience developing DFT specifications and driving DFT architecture and methods for designs.
Proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon.
Proficient in a scripting language such as Python, TCL, or Perl, including familiarity or proficiency in leveraging generative AI tools to accelerate scripting and engineering workflows.
Ability to fluently speak and write in English, including expressing complex technical concepts clearly.

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Industry: Technology: Manufacturing

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