CPU MicroArchitect / RTL Engineer - Site Lead
29 days ago Beaverton, OR
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Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced technical leader and manager to drive microarchitecture and RTL development in multiple areas of our performant cores, leading the CPU RTL team at this growing site.
Description
As a CPU MicroArchitect / RTL Engineer, you will own or participate in the following:
• Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Validation - support test bench development and simulation for functional and performance verification
• Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
• Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power
Preferred Qualifications
Previous experience leading a team of senior engineers to deliver complex microarchitecture definition and RTL development, including direct individual technical contribution
Record of mentoring and supporting the career development of other engineers
Expertise in one or more of the following areas of microprocessor architecture: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, cache and memory subsystems - advanced understanding in multiple areas a plus: Understanding of low power microarchitecture techniques. Understanding of high performance techniques and trade-offs in a CPU microarchitecture. Experience in C or C++ programming. Experience using an interpretive language such as Perl or Python.
Minimum Qualifications
Minimum BS and 15+ years of relevant industry experience
Knowledge of microprocessor architecture
Knowledge of Verilog and/or VHDL
Experience with simulators and waveform debugging tools
Knowledge of logic design principles along with timing and power implications
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced technical leader and manager to drive microarchitecture and RTL development in multiple areas of our performant cores, leading the CPU RTL team at this growing site.
Description
As a CPU MicroArchitect / RTL Engineer, you will own or participate in the following:
• Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Validation - support test bench development and simulation for functional and performance verification
• Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
• Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power
Preferred Qualifications
Previous experience leading a team of senior engineers to deliver complex microarchitecture definition and RTL development, including direct individual technical contribution
Record of mentoring and supporting the career development of other engineers
Expertise in one or more of the following areas of microprocessor architecture: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, cache and memory subsystems - advanced understanding in multiple areas a plus: Understanding of low power microarchitecture techniques. Understanding of high performance techniques and trade-offs in a CPU microarchitecture. Experience in C or C++ programming. Experience using an interpretive language such as Perl or Python.
Minimum Qualifications
Minimum BS and 15+ years of relevant industry experience
Knowledge of microprocessor architecture
Knowledge of Verilog and/or VHDL
Experience with simulators and waveform debugging tools
Knowledge of logic design principles along with timing and power implications
Additional Information
- Posted: 29 days ago