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Apple

Design Verification Engineer

Oct 3, 2026• Flexible / Remote

About us

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.

★ 3.7 out of 5 · 120 reviews

  • Size: 10,000+ employees
  • Industry: Technology: Manufacturing
View company profile ›

Why you should apply for a job to Apple:

  • Ranked as one of the Best Technology Companies in 2020
  • 3.7/5 in overall job satisfaction
  • 3.1/5 in supportive management
  • 66% say women are treated fairly and equally to men
  • 65% would recommend this company to other women
  • 66% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure, and for project execution for the next generation Apple high-speed interfaces to enable groundbreaking I/O connectivity solutions for Apple product lines.
You will have regular interaction with Architecture, Design and SW teams, and the opportunity to influence our future products.
The people who work here have reinvented entire industries with all Apple hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products.

Description
You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post-Silicon Validation.

Preferred Qualifications
B.Sc / M.Sc in Electrical or Computer Engineering

Minimum Qualifications
+6 years of experience in SoC Verification
You will need to have advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows, and a broad system view
Expected to have a deep understanding and shown experience in advanced verification processes, including dynamic, coverage-based, and formal methods
Extensive experience with System Verilog or UVM
Experience with verification infrastructure development
Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL - an advantage

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Additional Information

  • Posted: Oct 3, 2026
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