Lead Application Engineer
8 days ago Zhubei, Taiwan
About us
Cadence is a pivotal leader in computational software.
- Size: 10,000+ employees
- Industry: Technology: Manufacturing
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities:
• Engage with customers to understand verification challenges and identify suitable AI-assisted verification use cases. - UVM testbench and component generation - Test and sequence generation - VIP integration and configuration - Assertion and functional coverage generation - Simulation failure triage and root-cause analysis - Log and waveform analysis - Verification flow automation
• Develop and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC designs.
• Develop reusable prompts, skills, agents, scripts, and AI-assisted workflows for customer applications.
• Conduct technical evaluations, benchmarks, demonstrations, workshops, and customer training.
• Troubleshoot UVM, simulation, AI integration, and verification flow issues.
• Collaborate with R&D, Product Engineering, and support teams to address customer requirements and technical issues.
• Develop technical collateral, AI use cases, reference flows, and best practices.
Qualifications:
• MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Five or more years of experience in digital design, functional verification, or EDA application engineering.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience developing UVM environments, including agents, sequences, scoreboards, reference models, functional coverage, and register models.
• Strong understanding of constrained-random and coverage-driven verification methodologies.
• Experience integrating and debugging Verification IP in UVM-based environments.
• Experience with simulation, debug, coverage analysis, or low-power verification.
• Experience with Cadence tools such as Xcelium, Verisium, or VIP is a strong advantage.
• Strong scripting skills in Python, TCL, shell scripting, or Perl.
• Ability to translate verification challenges into practical and measurable AI-assisted solutions.
• Strong problem-solving, communication, presentation, and customer engagement skills.
Preferred Qualifications:
• Experience architecting reusable UVM environments for complex SoC or subsystem verification.
• Experience applying AI or automation to testbench generation, sequence generation, coverage, debug, or regression analysis.
• Familiarity with LLM APIs, prompt engineering, RAG, vector databases, agent-based workflows, MCP, or tool-calling frameworks.
• Experience deploying AI solutions in cloud-based or on-premises environments.
• Knowledge of CPU, interconnect, memory subsystem, low-power, or UPF verification.
• Familiarity with one or more protocols, including: - AMBA CHI, AXI, or AHB - USB or USB4 - LPDDR or HBM - UFS, UniPro, or M-PHY - PCI Express - DisplayPort or eMMC
We're doing work that matters. Help us solve what others can't.
Responsibilities:
• Engage with customers to understand verification challenges and identify suitable AI-assisted verification use cases. - UVM testbench and component generation - Test and sequence generation - VIP integration and configuration - Assertion and functional coverage generation - Simulation failure triage and root-cause analysis - Log and waveform analysis - Verification flow automation
• Develop and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC designs.
• Develop reusable prompts, skills, agents, scripts, and AI-assisted workflows for customer applications.
• Conduct technical evaluations, benchmarks, demonstrations, workshops, and customer training.
• Troubleshoot UVM, simulation, AI integration, and verification flow issues.
• Collaborate with R&D, Product Engineering, and support teams to address customer requirements and technical issues.
• Develop technical collateral, AI use cases, reference flows, and best practices.
Qualifications:
• MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Five or more years of experience in digital design, functional verification, or EDA application engineering.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience developing UVM environments, including agents, sequences, scoreboards, reference models, functional coverage, and register models.
• Strong understanding of constrained-random and coverage-driven verification methodologies.
• Experience integrating and debugging Verification IP in UVM-based environments.
• Experience with simulation, debug, coverage analysis, or low-power verification.
• Experience with Cadence tools such as Xcelium, Verisium, or VIP is a strong advantage.
• Strong scripting skills in Python, TCL, shell scripting, or Perl.
• Ability to translate verification challenges into practical and measurable AI-assisted solutions.
• Strong problem-solving, communication, presentation, and customer engagement skills.
Preferred Qualifications:
• Experience architecting reusable UVM environments for complex SoC or subsystem verification.
• Experience applying AI or automation to testbench generation, sequence generation, coverage, debug, or regression analysis.
• Familiarity with LLM APIs, prompt engineering, RAG, vector databases, agent-based workflows, MCP, or tool-calling frameworks.
• Experience deploying AI solutions in cloud-based or on-premises environments.
• Knowledge of CPU, interconnect, memory subsystem, low-power, or UPF verification.
• Familiarity with one or more protocols, including: - AMBA CHI, AXI, or AHB - USB or USB4 - LPDDR or HBM - UFS, UniPro, or M-PHY - PCI Express - DisplayPort or eMMC
We're doing work that matters. Help us solve what others can't.
Additional Information
- Posted: 8 days ago