Lead Software Engineer - Logic Synthesis
Sep 8, 2026 Shanghai, China
About us
Cadence is a pivotal leader in computational software.
- Size: 10,000+ employees
- Industry: Technology: Manufacturing
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Position Description:
Position Requirement:
We're doing work that matters. Help us solve what others can't.
Position Description:
- Responsible for development and maintenance of the synthesizer for Palladium.
- Implementation for new VHDL/Verilog feature support in synthesizer.
- Logic optimization and performance improvement in synthesizer.
Position Requirement:
- This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience.
- Candidate should be proficient with C/C++, Operating system concepts.
- Design modeling using Verilog/SV, VHDL or SysC.
- Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable.
- EDA/CAD tool development experience or logic design verification experience is highly preferred.
- Knowledge and experience in AI tools like Copilot or Claude code is preferred.
- Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project.
We're doing work that matters. Help us solve what others can't.
Additional Information
- Posted: Sep 8, 2026