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Cadence Design Systems

Sr Principal Design Engineer

Sep 3, 2025• Bangalore, India

About us

Cadence is a pivotal leader in computational software.

★ 4.4 out of 5 · 53 reviews

  • Size: 10,000+ employees
  • Industry: Technology: Manufacturing
View company profile ›

Why you should apply for a job to Cadence Design Systems:

  • Ranked as one of the Best Technology Companies in 2024
  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Summary

We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.

Key Responsibilities

  • Architect and implement RTL for PCIe IP blocks
  • Collaborate with system architects to define micro-architecture and design specifications.
  • Responsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must.
  • Work closely with verification teams to develop testbenches and validate functionality.
  • Participate in interoperability testing
  • Contribute to performance, power, and area optimization in advanced nodes.
  • Interface with cross-functional teams including PHY, software, and validation.

Required Skills

  • Strong hands-on experience in RTL design using Verilog/SystemVerilog.
  • Deep understanding of PCIe protocol stack and transaction layers.
  • Experience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling,
  • Familiarity with CDC design principles and asynchronous FIFO implementation.
  • Proficiency in synthesis, linting, and static timing analysis.
  • Exposure to formal verification and assertion-based design methodologies.
  • Experience with simulation tools and waveform debugging.

Education

  • Bachelor's or Master's degree in Electronics /Electrical Engineering , or related field.

We're doing work that matters. Help us solve what others can't.

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Additional Information

  • Posted: Sep 3, 2025
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