2 jobs for "Intern on AMS tool in Milan"

Formal Verification Framework for Hardware IPs Validation

At Apple - London

Posted on Oct 19

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Creator Operations Project Intern (TikTok Shop Italy) - 2026 Start (BS/MS)

At TikTok - Milan

Posted on Nov 9

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Apple

Formal Verification Framework for Hardware IPs Validation

London, United KingdomPosted 22 days ago

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Join a rapidly growing team at our London design center. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly.
The AMS IP team owns a wide portfolio of IPs & complete subsystems going to all the Apple products. In this context the Design Verification Engineer will have to interface with many different teams at Apple and build knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to-end: starting at the specification level, defining the verification strategy & plan, executing the verification, doing performance analysis and handling all the different quality metrics to signoff the verification.

Description
Define comprehensive property sets for functional coverage of hardware models
Formalize verification properties using SVA
Execute formal proofs and analyze convergence behavior (accuracy VS execution time)
Document methodology and best practices for the verification flow","responsibilities":"This internship would require a strong foundation in formal verification methodologies, good mathematical reasoning as well as some knowledge in hardware modeling. The intern will work on developing comprehensive property sets to achieve functional coverage of hardware models. The focus will be on formalizing properties in SVA and executing formal proofs using industry-standard tools. A key challenge will be identifying optimal trade-offs between model accuracy and proof convergence times.
The intern will then extend the verification framework in order to integrate the properties at higher levels to enable system verification.

Preferred Qualifications
Master's / Bachelor's in Computer Science or equivalent
You are available for 6 months or more

Minimum Qualifications
Currently enrolled in Computer Science or equivalent
Knowledge of formal verification techniques
Knowledge of Verilog and/or VHDL
Passionate about mathematics, and good mathematical/analytical sense
Scripting language knowledge (perl/python)
Good written and verbal communication skills
Experience in working with international teams

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Industry: Technology: Manufacturing

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