16 jobs for "Standard Cell Design Methodology & Flow Engineer"

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CPU Physical Design Engineer

At Apple - Beaverton

Posted on Oct 15

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CPU Implementation Engineer

At Apple - Beaverton

Posted on Oct 12

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CPU Implementation Engineer

At Apple - Beaverton

Posted on Oct 12

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At Apple - Santa Clara

Posted on Oct 12

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CPU Implementation Engineer

At Apple - Santa Clara

Posted on Oct 12

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Customer Engagement Engineer II - Xcelium

At Cadence Design Systems - Seoul

Posted on Oct 22

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Consultant, Tax Content Architect

At Cargill - Bengaluru

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CPU Physical Electrical Analysis Engineer

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CPU Physical Electrical Analysis Engineer

At Apple - Beaverton

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Physical Design Lead - Custom Silicon Management

At Apple - Austin

Posted on Oct 19

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Physical Design Lead - Custom Silicon Management

At Apple - Austin

Posted on Oct 19

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Physical Design Lead - Custom Silicon Management

At Apple - Austin

Posted on Oct 19

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Cadence Design Systems

Customer Engagement Engineer II - Xcelium

SeoulPosted 17 days ago

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Work with R&D to identify and scope opportunities for the Cadence functional logic verification platform
Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
Summarize the tasks and projects, and report to manager and share with team effectively
Train, ramp-up and accompany customer project.
Conduct basic and advanced trainings, presentations and demos as necessary.
Ramp-up other members of the team on the advanced verification technologies and tools.
Providing technical expertise to address clients' queries, which need expert involvement

The candidate should possess minimum BS level of CS or EE with 3-5 years of industry experience.
Minimum 3 years hands-on, high expertise on hardware design & verification techniques.
Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.
Experience of RTL design or verification with Verilog / SV Language or C/C++ or System C.
Understanding standard BUS protocol like AMBA or interface protocol.
Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC.
Experience on UVM methodology or similar one should be preferred.
Hands on Design experience using SystemVerilog, Verilog and VHDL.
Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies.
Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.
Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.
Good communication skills in English and a strong desire for working in a global environment with customers and BU people.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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