157 jobs for "Physical Design Signoff Engineer"

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Group Director, Design Engineering - Front End

At Cadence Design Systems - Austin

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At Cadence Design Systems - San Jose

Posted on Sep 11

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At Cadence Design Systems - San Jose

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CPU Full-chip Physical Integration Engineer

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CPU Physical Design and Integration Engineer

At Apple - Santa Clara

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At Apple - Austin

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SoC Physical Design Engineer, PnR

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Posted on Oct 14

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Timing Design Engineer

At Apple - San Diego

Posted on Oct 14

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GPU Physical Design Engineer, STA/Timing

At Apple - Austin

Posted on Oct 14

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CPU Full Chip Physical Integration Engineer

At Apple - Austin

Posted on Oct 10

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Timing Design Engineer

At Apple - Beaverton

Posted on Oct 8

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Timing Design Engineer

At Apple - Waltham

Posted on Oct 8

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Sr Application Engineer

At Cadence Design Systems - Bangalore

Posted on Apr 29

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AMS STA / Timing Engineer (m/f/d)

At Apple - München

Posted on Oct 7

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AI Methodology Design/CAD Engineer

At Apple - Austin

Posted on Oct 3

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GPU Physical Design Engineer

At Apple - Austin

Posted on Oct 19

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Jun 18

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Cadence Design Systems

Lead Design Engineer

Pune, IndiaPosted Jun 18, 2026

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities:

The Candidate will have design responsibility, including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power / EM-IR signoff, physical verification (DRC/LVS/Antenna), and DFM Closure.
Physical design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools
Physical design for PPA optimization of performance and power-oriented best-in-class interface IPs such as DDR, LPDDR, PCIE, UCIE, etc and test chips for advanced process nodes, such as 7nm/5nm/3nm/2nm
An opportunity to work on many varieties of challenging designs, i.e., low power, high-speed and area optimized designs.
Work closely with RTL design team & Analog Team to ensure on-time, successful tapeouts.

Required skills -

B.Tech/BE/ME/Mtech with 4-6 years hands-on experience in physical design and physical verification.
Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
Solid knowledge on physical design, static timing analysis, Low Power Design, EM/IR /crosstalk analysis, formal verification, physical verification, DFM, DFT.
Successful track records of taping out complex IP's & SoC's at 16/10/7/5/3 nm with different foundries.
Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus will be an added advantage
Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/python assisted with AI.
Should have excellent communication, analytical and problem-solving skills, should be self-motivated and good team player

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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