1,108 jobs for "Design Verification Engineer"

Customer Engagement Architect

At Cadence Design Systems - San Jose

Posted on Sep 23

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Lead Customer Engagement Engineer

At Cadence Design Systems - San Jose

Posted on Sep 23

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Lead Customer Engagement Engineer

At Cadence Design Systems - San Jose

Posted on Sep 23

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Customer Engagement Engineer II

At Cadence Design Systems - San Jose

Posted on Sep 23

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SoC Design and Integration Engineer

At Apple - Cupertino

Posted on Oct 14

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SoC Physical Design Engineer - Power Delivery

At Apple - Austin

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SoC Physical Design Engineer - Power Delivery

At Apple - Austin

Posted on Oct 14

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SoC Physical Design Engineer - Power Delivery

At Apple - Austin

Posted on Oct 14

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Design Engineer II

At Cadence Design Systems - Austin

Posted on Sep 25

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SoC FE Implementation Engineer

At Apple - Cupertino

Posted on Oct 19

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SoC FE Implementation Engineer

At Apple - Cupertino

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Senior Systems Engineer

At Leidos - Laurel

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Lead Design Engineer

At Cadence Design Systems - Austin

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Design Engineering Architect - Systems and Interfaces

At Cadence Design Systems - San Jose

Posted on Nov 4

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Lead Digital Verification Engineer

At Cadence Design Systems - Mount-royal

Posted on Nov 3

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Senior Systems Engineer - Verification

At Leidos - Huntsville

Posted on Nov 3

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Design Engineer II

At Cadence Design Systems - Bangalore

Posted on Oct 29

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Firmware Engineer II

At Cadence Design Systems - Bangalore

Posted on Oct 29

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Firm ware Engineer II

At Cadence Design Systems - Bangalore

Posted on Oct 29

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SoC Physical Design Engineer (M, F, D)

At Apple - München

Posted on Oct 19

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Cadence Design Systems

Lead Design Engineer

AustinPosted yesterday

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

#### Responsibilities:

* Design and integration of IPs in SoC based on high-level architectural specifications from customers.
* Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
* Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
* Create detailed Microarchitectural Specification documents for the design.
* Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
* Provide support to the physical design team as needed for design implementation.
* Implement innovative solutions to automate repetitive tasks.
* Collaborate within and across teams for effective project execution.

#### Requirements:

* B.E./B.Tech/M.Tech with 5-8 years of experience as a digital design engineer.
* Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
* Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
* Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
* Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
* Experience with AMBA protocols and other ARM IPs is a plus.
* Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
* Proficiency in scripting languages (Python/Perl/Tcl).
* Ability to innovate and automate repetitive tasks.
* Good communication skills for effective cross-functional collaboration.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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