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Cadence Design Systems

Sr Principal Verification Engineer

Shanghai, ChinaPosted Aug 24, 2026

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Qualifications

Minimal qualification requires BS/MS degree EE or CS with [ 5-7+ years (T4) ] of experience in relevant experience.

As a [Principal Verification Engineer (T4) ] you will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM (LPDDRx, DDRx, HBMx), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products.

• Must analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support.

• Must analyze product-wide feature requirements and execute on their verification.

• Must integrate additional related tools and processes-including coverage, reporting, and regressing-to build a robust team-level verification structure and competence.

Additional responsibilities include the following:

• Researching tools, languages, methodologies and prototype processes to enhance product verification as well as to demonstrate product quality.

• Updating, enhancing, maintaining, and supporting existing system level UVM test environments for memory model products.

• Supporting product (IP Library) regression, OS compliance, process automation, and product release preparation as needed.

Job Responsibilities & Skills: [Principal Verification Engineer (T4) ]

• Candidate must be an Electrical, Electronics or Computer Science Engineer with expert understanding of HDLs and HVLs such as Verilog and SystemVerilog.

• Solid experience in simulation/emulation using these languages. He/ she should have expert working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools.

• Deep experience with UVM, SystemVerilog, and C++.

• Must have solid, deep experience on multiple protocols such as UFS Unipro and MPHY, SDRAM, Ethernet, PCIe, USB3/4, MIPI etc

• Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.

• Experience with Functional Verification of complex protocol-based blocks-e.g. UFS / Unipro/ MPHY verification-with a Hardware Verification Language (HVL) like SystemVerilog.

• Experience designing and implementing complex functional verification environments is required.

• Experience in process automation with scripting is required.

Behavioral skills required.

• Possess very strong English verbal and written skills.

• Ability to establish close, collaborative working relationships with team colleagues, peers, customers, vendors, and management.

• Likewise, the ability to execute with strong individual and independent R&D skills.

• Motivation and capacity to mentor less experienced engineers and to participate in cross-functional projects.

• Explore what's possible to complete a committed job while maintaining high product quality.

• Work effectively across functions and geographies.

• Participate in team processes; evaluate and recommend process improvements.

Strongly recommended:

• Verification experience using Cadence simulation and/or emulation products is highly desired.

• Experience in memory sub-system or controller verification and operation is strongly recommended.

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About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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