437 jobs for "SOC Design Verification Engineer"

SoC DFT DV Engineer

At Apple - Austin

Posted on Oct 11

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SoC DFT DV Engineer

At Apple - Austin

Posted on Oct 11

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SoC DFT DV Engineer

At Apple - Austin

Posted on Oct 11

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GPU Power and Performance Characterization Engineer

At Apple - Austin

Posted on Oct 9

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Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jul 23

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Lead Solutions Engineer

At Cadence Design Systems - Bangalore

Posted on May 1

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Principal Software Engineer

At Cadence Design Systems - Noida

Posted on Oct 28

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Software Engineer II

At Cadence Design Systems - Noida

Posted on Oct 7

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Principal Design Engineer

At Cadence Design Systems - San Jose

Posted on Oct 9

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Lead Design Engineer

At Cadence Design Systems - Cary

Posted on Jul 22

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CAD Engineer - Timing for Gate-Level Flows & Methodologies

At Apple - Austin

Posted on Oct 17

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CAD Engineer - Timing for Gate-Level Flows & Methodologies

At Apple - Austin

Posted on Oct 17

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SoC Pre-Silicon Platform Engineering Program Manager

At Apple - Cupertino

Posted on Oct 17

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SoC UPF Methodology Engineer

At Apple - Austin

Posted on Oct 17

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SoC UPF Methodology Engineer

At Apple - Austin

Posted on Oct 17

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SoC UPF Methodology Engineer

At Apple - Austin

Posted on Oct 17

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SoC UPF Methodology Engineer

At Apple - Austin

Posted on Oct 17

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CPU Verification Engineer

At Apple - Herzliya

Posted on Oct 6

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CPU Verification Engineer

At Apple - Herzliya

Posted on Oct 6

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Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 9

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Cadence Design Systems

Lead Design Engineer

Hyderabad, IndiaPosted Aug 9, 2026

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Development, automation and maintenance of EDA flows and scripts for physical implementation
Develop TFM to optimize PPA for IP's and Soft Controllers
PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
Required skills -
Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years' experience
Physical design experience in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
Should have excellent leadership, communication, analytical and problem solving skills.
Expertise on High frequency design methodologies for complete ASIC backend flows.
Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
Solid scripting skills including Python and Tcl.
Should be self-motivated and good team player.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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