45 jobs for "PHY RTL Design Engineer"

PHY RTL Design Engineer

At Apple - Irvine

Posted on Oct 12

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PHY RTL Design Engineer

At Apple - Irvine

Posted on Oct 12

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PHY RTL Design Engineer

At Apple - Irvine

Posted on Oct 12

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PHY Design Verification Engineer

At Apple - San Francisco Bay Area

Posted on Oct 19

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PHY Design Verification Engineer

At Apple - San Francisco Bay Area

Posted on Oct 19

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PHY Design Verification Engineer

At Apple - San Francisco Bay Area

Posted on Oct 17

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PHY Design Verification Engineer

At Apple - San Francisco Bay Area

Posted on Oct 17

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PHY Design Verification Engineer

At Apple - San Francisco Bay Area

Posted on Oct 17

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Principal Design Engineer

At Cadence Design Systems - Dublin

Posted on Sep 22

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Principal Design Engineer

At Cadence Design Systems - Remote / Flexible

Posted on Feb 24

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Sr Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Sep 3

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Experienced AMS Digital Design Engineer

At Apple - London

Posted on Oct 17

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Physical Design Engineer

At Apple - Beaverton

Posted on Oct 17

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IP Logic Design Engineer - Advanced Technologies Group

At Apple - Haifa

Posted on Oct 16

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Physical Design Engineer

At Apple - San Francisco Bay Area

Posted on Oct 14

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Experienced AMS Digital Design Engineer (m/f/d)

At Apple - München

Posted on Oct 7

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Physical Design Engineer

At Apple - Cupertino

Posted on Oct 17

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Physical Design Engineer

At Apple - Cupertino

Posted on Oct 17

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Physical Design Engineer

At Apple - Cupertino

Posted on Oct 17

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Physical Design Engineer

At Apple - Cupertino

Posted on Oct 17

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Cadence Design Systems

Sr Principal Design Engineer

Bangalore, IndiaPosted Sep 3, 2025

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Summary

We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.

Key Responsibilities

Architect and implement RTL for PCIe IP blocks
Collaborate with system architects to define micro-architecture and design specifications.
Responsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must.
Work closely with verification teams to develop testbenches and validate functionality.
Participate in interoperability testing
Contribute to performance, power, and area optimization in advanced nodes.
Interface with cross-functional teams including PHY, software, and validation.

Required Skills

Strong hands-on experience in RTL design using Verilog/SystemVerilog.
Deep understanding of PCIe protocol stack and transaction layers.
Experience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling,
Familiarity with CDC design principles and asynchronous FIFO implementation.
Proficiency in synthesis, linting, and static timing analysis.
Exposure to formal verification and assertion-based design methodologies.
Experience with simulation tools and waveform debugging.

Education

Bachelor's or Master's degree in Electronics /Electrical Engineering , or related field.

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About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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