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Principal Product Engineer - DIP

At Cadence Design Systems - Shanghai

Posted on Aug 7

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Signal Integrity Engineer - Memory Interface

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Signal Integrity Engineer - Memory Interface

At Apple - San Francisco Bay Area

Posted on Oct 19

View job Apply on company site

Cadence Design Systems

Principal Product Engineer - DIP

Shanghai, ChinaPosted Aug 7, 2026

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

Technical Support & Case Management: Act as the primary interface for technical issues, driving resolution for complex subsystem application or implementation problems. This includes monitoring case management systems like Salesforce (SFDC) and Jira.
IP Integration & Validation: Support Pre-Silicon integration, post-silicon bring-up, and verification of PHY and controller SoC integration. Conduct RTL and gate-level simulations to ensure functionality and assist with timing closure.
Customer Engagement: Proactively engage with customers to identify potential issues, prioritize critical technical problems, and manage escalations, ensuring high satisfaction.
Technical Leadership: Develop comprehensive knowledge bases, document product limitations, and provide feedback to internal Product Engineering and R&D teams for continuous improvement.
Guidance & Training: Create and deliver technical training, seminars, and documentation to support customer success and adoption of best practices.

Required Qualifications

Experience: Requires 8+ years of experience in verification and design, specifically with IP development.
Technical Expertise: Strong background in digital electronics, Verilog/SystemVerilog, and UVM methodology.
Protocol Knowledge: Practical knowledge of memory or communication interface IP protocols such as MIPI (CSI2/DSI/I3C/PHY), PCI Express, DDR, LPDDR, HBM, or USB.
Skills: Excellent debugging skills, ability to handle complex problems, and proficiency in scripting languages (TCL, Perl, or Python).
Education: Bachelor's or Master's in Electronics or Electrical Engineering.

Preferred Skills

Experience with Cadence-specific tools, EDA workflows, or similar IP design platforms.

Core Competencies

Strong communication and presentation skills, capable of influencing both internal teams and customer stakeholders.
Proactive and collaborative approach, able to work across global, cross-functional teams.
Strategic thinking to drive product roadmap improvements based on user feedback.
Fluent spoken English

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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