29 jobs for "Mixed Signal RTL Design Engineer"

GPU Top Level Physical Design Engineer

At Apple - Cambridge

Posted on May 28

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RTL Design Engineer

At Apple - Melbourne

Posted on Oct 17

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RTL Design Engineer

At Apple - Waltham

Posted on Oct 17

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GPU Top Level Physical Design Engineer

At Apple - Austin

Posted on Oct 14

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GPU Top Level Physical Design Engineer

At Apple - Austin

Posted on Oct 14

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GPU Top Level Physical Design Engineer

At Apple - Austin

Posted on Oct 14

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IP Integration Engineer

At Apple - San Francisco Bay Area

Posted on Oct 9

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GPU Top Level Physical Design Engineer

At Apple - Cambridge

Posted on May 28

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Mixed Signal IP - Senior Program Manager

At Cadence Design Systems - San Jose

Posted on Oct 16

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Apple

GPU Top Level Physical Design Engineer

Cambridge, United KingdomPosted May 28, 2026

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Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU. You will ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.

Join us!

Description
As a GPU Top Level Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the physical design team, as you develop methodologies and "best known methods" that'll enable best-in-class GPU design. You will develop PD guidelines and checklists, drive execution, and supervise progress. Be the focal point for place and route integration at the top level. You will need to communicate and drive the needs of PD with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Preferred Qualifications
Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.
Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs.
Understanding of GPU architecture and design units.
Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.

Minimum Qualifications
Minimum of BSc in EE and some relevant experience.
Experience with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.

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Industry: Technology: Manufacturing

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