169 jobs for "ASIC Design Engineer"

Responsibilities

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

Responsibilities:
- Responsible for the architecture design, development, implementation, and integration of NoC (Network-on-Chip) systems.
- Collaborate with the verification team to ensure the functional correctness and performance targets of the NoC.
- Work with the backend/physical implementation team to ensure that the NoC's physical implementation meets design goals.

Qualifications

Minimum Qualification(s)
- Bachelor's degree or above in Microelectronics, Computer Science, or a related field; 4+ years of experience in bus/interconnect development.
- Solid understanding of computer architecture; experience in large-scale SoC chip design; proficiency in at least one commercial NoC/bus IP, such as FlexNoC or NIC.
- Proficiency in common bus protocols, such as AMBA AXI, APB, and AHB.
- Strong foundation in logic design and RTL coding; experience with a complete front-end design flow; familiarity with common EDA tools and with Lint, CDC, Synthesis, and STA.
- Familiarity with scripting languages commonly used in design flows, such as Python, TCL, and Perl; familiarity with common IPs in SoC systems and with clock/reset design.
- Strong logical thinking, communication and presentation skills, and a collaborative team spirit; honest and upright.

Preferred Qualification(s)
- Familiarity with the architecture, protocols, and complex data flows of core SoC subsystems (e.g., CPU/NPU clusters, Memory subsystems, NoC).
- Hands-on experience with Hardware Emulation (Palladium, ZeBu) or FPGA prototyping platforms.
- Proficiency in Formal Verification methodologies and tools (e.g., JasperGold).
- Experience in SoC-level Performance and Power-Aware (PA) verification.

Job Information

[For Pay Transparency] Compensation Description (annually)

The base salary range for this position in the selected city is $162000 - $316800 annually.

Compensation may vary outside of this range depending on a number of factors, including a candidate's qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.

Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure).

The Company reserves the right to modify or change these benefits programs at any time, with or without notice.

For Los Angeles County (unincorporated) Candidates:

Qualified applicants with arrest or conviction records will be considered for employment in accordance with all federal, state, and local laws including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Our company believes that criminal history may have a direct, adverse and negative relationship on the following job duties, potentially resulting in the withdrawal of the conditional offer of employment:

1. Interacting and occasionally having unsupervised contact with internal/external clients and/or colleagues;

2. Appropriately handling and managing confidential information including proprietary and trade secret information and access to information technology systems; and

3. Exercising sound judgment.

Responsibilities

Qualifications

Qualifications

Minimum Qualification(s)
- Bachelor's degree or above in Microelectronics, Computer Science, or a related field; 4+ years of experience in bus/interconnect development.
- Solid understanding of computer architecture; experience in large-scale SoC chip design; proficiency in at least one commercial NoC/bus IP, such as FlexNoC or NIC.
- Proficiency in common bus protocols, such as AMBA AXI, APB, and AHB.
- Strong foundation in logic design and RTL coding; experience with a complete front-end design flow; familiarity with common EDA tools and with Lint, CDC, Synthesis, and STA.
- Familiarity with scripting languages commonly used in design flows, such as Python, TCL, and Perl; familiarity with common IPs in SoC systems and with clock/reset design.
- Strong logical thinking, communication and presentation skills, and a collaborative team spirit; honest and upright.

Preferred Qualification(s)
- Familiarity with the architecture, protocols, and complex data flows of core SoC subsystems (e.g., CPU/NPU clusters, Memory subsystems, NoC).
- Hands-on experience with Hardware Emulation (Palladium, ZeBu) or FPGA prototyping platforms.
- Proficiency in Formal Verification methodologies and tools (e.g., JasperGold).
- Experience in SoC-level Performance and Power-Aware (PA) verification.

About TikTok

TikTok is the leading destination for short-form mobile video and our mission is to inspire creativity and bring joy.

Size: 10,000+ employees
Industry: Technology: Consumer Internet

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