38 jobs for "Gate-level IR/EM CAD/NLP Engineer"

Lead Design Engineer

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Software Engineer - Intern (TikTok BRIC) - 2027 Start (PhD)

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Full-stack Engineer 5 (Sr. Lead / Sr. Manager IC)

At Capital One - McLean · Richmond

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At Capital One - McLean · San Francisco

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Full-stack Engineer 4

At Capital One - Plano

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Full-stack Engineer 4 (Global Payment Network)

At Capital One - Riverwoods · Chicago

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Full-stack Engineer 5

At Capital One - Plano

Posted on Nov 8

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Full-stack Engineer 4

At Capital One - Richmond

Posted on Nov 8

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Senior Director, AI Engineering -Agentic AI Platform(Remote Eligible)

At Capital One - Remote / Flexible

Posted on Nov 8

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Full-stack Engineer 4

At Capital One - Plano

Posted on Nov 8

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Cadence Design Systems

Lead Design Engineer

AustinPosted today

Apply on company site View full job

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

#### Responsibilities:

* Design and integration of IPs in SoC based on high-level architectural specifications from customers.
* Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
* Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
* Create detailed Microarchitectural Specification documents for the design.
* Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
* Provide support to the physical design team as needed for design implementation.
* Implement innovative solutions to automate repetitive tasks.
* Collaborate within and across teams for effective project execution.

#### Requirements:

* B.E./B.Tech/M.Tech with 5-8 years of experience as a digital design engineer.
* Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
* Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
* Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
* Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
* Experience with AMBA protocols and other ARM IPs is a plus.
* Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
* Proficiency in scripting languages (Python/Perl/Tcl).
* Ability to innovate and automate repetitive tasks.
* Good communication skills for effective cross-functional collaboration.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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