13 jobs for "STA & Custom Logic Design Engineer"

STA Application Engineer

At Cadence Design Systems - San Jose

Posted on Nov 6

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Lead Design Engineer

At Cadence Design Systems - Austin

Posted on Nov 7

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Principal AE (STA - SignOff)

At Cadence Design Systems - Austin

Posted on Nov 6

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IC design Implementation and SignOff Architect, (STA SignOff)

At Cadence Design Systems - Remote / Flexible

Posted on Nov 6

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Principal Application Engineer

At Cadence Design Systems - San Jose

Posted on Nov 6

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Expression Of Interest - Senior Project Engineer - Malaysia

At Cummins - Johor Bahru

Posted on Nov 2

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Manager, Security Capability Owner - Identity & Access

At Nike - Beaverton

Posted on Nov 4

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Manutentore Elettrico e Sistemi Condizionamento (Data Center Critical Facilities IV)

At Equinix - Milan

Posted on Nov 6

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RTL2GDS Principal AE

At Cadence Design Systems - San Jose

Posted on Nov 6

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STA Signoff Flow, Principal AE

At Cadence Design Systems - San Jose

Posted on Nov 6

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Application Engineer

At Cadence Design Systems - San Jose

Posted on Nov 6

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Sr Principal Application Engineer

At Cadence Design Systems - Austin

Posted on Nov 6

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Intern - Design Engineering

At Cadence Design Systems - Shanghai

Posted on Nov 5

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Cadence Design Systems

STA Application Engineer

San Jose$106,400 – $197,600Posted yesterday

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies.

Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows.

Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies.

Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.

Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts.

Execute and lead Tempus timing signoff campaigns at existing and new customers.

Automation of flows using scripting languages (Perl, Tcl, python).

Deliver technical trainings and seminars within Cadence and customer sites.

The annual salary range for California is $106,400 to $197,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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