22 jobs for "Design Verification Engineer for Cellular Baseband (m/f/d)"

lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Nov 3

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ECLSS Hardware Development Engineer

At Leidos - Webster

Posted on Nov 3

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Lead Design Engineer

At Cadence Design Systems - Austin

Posted on Nov 7

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Design Engineering Architect - Systems and Interfaces

At Cadence Design Systems - San Jose

Posted on Nov 4

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Senior Systems Engineer - Verification

At Leidos - Huntsville

Posted on Nov 3

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Lead Digital Verification Engineer

At Cadence Design Systems - Mount-royal

Posted on Nov 3

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Cloud/SecDevOps Engineer

At Leidos - Clarksburg

Posted on Nov 7

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Ingenieur Application departement Marin Cummins Saint - Herblain

At Cummins - Remote / Flexible

Posted on Nov 3

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Cleared Senior/Principal R&D Electrical Engineer - System Environmental Qualification Testing, Onsite

At Sandia National Laboratories

Posted on Nov 5

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Product Engineer

At Cummins - Cwmbran

Posted on Nov 3

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RTL2GDS Principal AE

At Cadence Design Systems - San Jose

Posted on Nov 6

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Principal Software Engineer

At Cadence Design Systems - Hsinchu

Posted on Nov 5

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Sr Surety Engineer

At Leidos - Albuquerque

Posted on Nov 5

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Firmware Engineer II

At Cadence Design Systems - Noida

Posted on Nov 4

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Sr Surety Engineer

At Leidos - Huntsville

Posted on Nov 5

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Systems Engineer

At Leidos - Remote / Flexible

Posted on Nov 5

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Lead Design Engineer

At Cadence Design Systems - Seoul

Posted on Nov 3

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Sr Design Engineer

At Cadence Design Systems - Seoul

Posted on Nov 3

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Lead Systems Engineer - Workforce Applications - Microsoft

At Enterprise Mobility - St. Louis

Posted on Nov 4

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Senior/Principal RD Systems Engineer - Surety Systems Engineering, Onsite

At Sandia National Laboratories

Posted on Nov 5

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Cadence Design Systems

Sr Design Engineer

SeoulPosted 6 days ago

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking talented Application Engineers dedicated for physical design in Cadence Korea. You will be responsible for the physical design implementation projects.
The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.

9+ experience with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
Able to assume responsibility for a variety of technical tasks and to work independently
Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
Self-motivated, able to work as a team player, and good English communication skills
The candidate will work closely with RTL design team to ensure successful tapeouts.

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About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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