169 jobs for "ASIC Design Engineer"

ASIC Design and Integration Engineer

At Apple - Beaverton

Posted on Oct 11

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ASIC Design and Integration Engineer

At Apple - Beaverton

Posted on Oct 11

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ASIC Design and Integration Engineer

At Apple - Beaverton

Posted on Aug 13

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ASIC Design and Integration Engineer

At Apple - Beaverton

Posted on Aug 13

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Design Engineer II

At Cadence Design Systems - Hyderabad

Posted on Aug 9

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Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 9

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Jun 18

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SoC Physical Design Engineer, Electrical Analysis

At Apple - Austin

Posted on Oct 17

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SoC Physical Design Engineer, Electrical Analysis

At Apple - San Diego

Posted on Oct 9

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SoC Physical Design Engineer, Top Level

At Apple - Beaverton

Posted on Sep 24

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SoC Physical Design Engineer, Electrical Analysis

At Apple - Austin

Posted on Oct 17

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SoC Physical Design Engineer - Power Delivery

At Apple - Austin

Posted on Oct 14

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Feb 19

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SoC Physical Design Engineer - Power Delivery

At Apple - Austin

Posted on Oct 14

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SoC Physical Design Engineer - Power Delivery

At Apple - Austin

Posted on Oct 14

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Mar 13

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SoC Physical Design Engineer, Electrical Analysis

At Apple - Austin

Posted on Oct 9

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SoC Physical Design Engineer, Electrical Analysis

At Apple - Austin

Posted on Oct 9

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SoC Physical Design Engineer, Top Level

At Apple - San Jose

Posted on Oct 1

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SoC Physical Design Engineer, Top Level

At Apple - Beaverton

Posted on Sep 24

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Cadence Design Systems

Design Engineer II

Hyderabad, IndiaPosted Aug 9, 2026

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
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87% say the CEO supports gender diversity

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Development, automation and maintenance of EDA flows and scripts for physical implementation
Develop TFM to optimize PPA for IP's and Soft Controllers
PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
Develop automation scripts using AI tools and reduce design execution turnaround time
Required skills -
Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years' experience
Physical design experience in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
Prior experience in Logic Synthesis and PPA optimization techniques, Logic Equivalence Checks ( LEC ) debug experience for production designs
A detailed understanding of synthesis flows, hands on experience in developing, debugging synthesis flows with EDA tools such as Genus, Fusion Compiler.
Should have excellent leadership, communication, analytical and problem solving skills
Solid scripting skills including Python and Tcl.
Should be self-motivated and good team player.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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