59 jobs for "DDR Design Engineer"

DDR Design Engineer

At Apple - Austin

Posted on Oct 14

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DDR Design Engineer

At Apple - San Diego

Posted on Oct 14

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DDR Design Engineer

At Apple - Beaverton

Posted on Oct 14

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DDR Design Engineer

At Apple - Waltham

Posted on Oct 9

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DDR Design Engineer

At Apple - Waltham

Posted on Oct 7

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Principal Product Engineer

At Cadence Design Systems - Shanghai

Posted on Aug 11

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Sr Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Aug 29

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Intern - Design Engineering

At Cadence Design Systems - Shanghai

Posted on Nov 5

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Design Engineer II

At Cadence Design Systems - Shanghai

Posted on Oct 26

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Principal Design Engineer - Physical Design

At Cadence Design Systems - Shanghai

Posted on Oct 6

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Jun 18

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Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Oct 10

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Oct 9

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Dec 12

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Lead Design Engineer

At Cadence Design Systems - Austin

Posted on Nov 7

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Wireless SOC Verification Engineer

At Apple - Irvine

Posted on Oct 19

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Design Engineering Architect - Systems and Interfaces

At Cadence Design Systems - San Jose

Posted on Nov 4

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Silicon Validation Engineer

At Apple - San Francisco Bay Area

Posted on Oct 19

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Signal Integrity Engineer - Memory Interface

At Apple - San Francisco Bay Area

Posted on Oct 19

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Design Engineer

At Cadence Design Systems - Shanghai

Posted on Oct 29

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Cadence Design Systems

Principal Design Engineer

Bangalore, IndiaPosted Oct 9, 2024

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Requirements
- M.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)
- Experience - 7+ years
- sound knowledge of DDR4/5, LPDDR4/5 IP.
- Hands on design/verification experience on DDR protocol
- Exposure to DDR Integration and Verification at SOC Level
- Exposure to Silicon Bring-up/Testing for DDR.
- Hands on design/verification experience on AMBA based protocols like AXI, AHB, APB
- Experience on cadence tools
- Exposure to Lint/CDC, Synthesis, Static Timing Analysis review
- Exposure to all major IC implementation, design, and verification tools.
- Willing to travel to customer sites worldwide.
- Working with global (US, west coast, and east coast) teams, which work in different time-zones.

Primary Responsibilities:
- Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
- Support DDR Controller and PHY SOC integration reviews, and integration questions.
- Perform RTL and gate level simulations to verify functionality.
- Assist customers with gate level simulations and timing closure.
- Participate in development of CDNS documentations and checklists for customers.
- Support post silicon bring-up and deployment activities by our customers.
- Enhance customer experience by providing prompt updates to customers.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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