339 jobs for "IP Design Verification Engineer"

Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Dec 18

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Feb 19

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SoC Physical Design Engineer, PnR

At Apple - Waltham

Posted on Oct 17

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SoC Physical Design Engineer, PnR

At Apple - Austin

Posted on Oct 8

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Design Engineer II

At Cadence Design Systems - Shanghai

Posted on Oct 26

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Principal Product Engineer - Memory IP

At Cadence Design Systems - Nanjing

Posted on Aug 18

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Senior Principal Design Engineer

At Cadence Design Systems - Nanjing

Posted on Oct 12

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Principal Design Engineer - Physical Design

At Cadence Design Systems - Shanghai

Posted on Oct 6

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Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 9

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Design Engineer II

At Cadence Design Systems - Hyderabad

Posted on Aug 9

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Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Sep 19

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DFT Engineer (M, F, D)

At Apple - Munich

Posted on Oct 17

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DFT Engineer (M, F, D)

At Apple - München

Posted on Oct 12

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Gate-level SigEM/SEB/FIT CAD Engineer

At Apple - Austin

Posted on Oct 19

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Gate-level SigEM/SEB/FIT CAD Engineer

At Apple - Austin

Posted on Oct 19

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Gate-level SigEM/SEB/FIT CAD Engineer

At Apple - Austin Metro Area

Posted on Oct 17

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Gate-level SigEM/SEB/FIT CAD Engineer

At Apple - Austin Metro Area

Posted on Oct 17

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Gate-level SigEM/SEB/FIT CAD Engineer

At Apple - Austin Metro Area

Posted on Oct 17

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Gate-level SigEM/SEB/FIT CAD Engineer

At Apple - Austin Metro Area

Posted on Oct 17

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Cadence Design Systems

Lead Design Engineer

Hyderabad, IndiaPosted Aug 9, 2026

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Development, automation and maintenance of EDA flows and scripts for physical implementation
Develop TFM to optimize PPA for IP's and Soft Controllers
PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
Required skills -
Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years' experience
Physical design experience in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
Should have excellent leadership, communication, analytical and problem solving skills.
Expertise on High frequency design methodologies for complete ASIC backend flows.
Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
Solid scripting skills including Python and Tcl.
Should be self-motivated and good team player.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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