186 jobs for "IP Design Verification Engineer"

Wireless SOC Verification Engineer

At Apple - Irvine

Posted on Oct 14

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Wireless SOC Verification Engineer

At Apple - Irvine

Posted on Oct 14

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Wireless SOC Verification Engineer

At Apple - Irvine

Posted on Oct 14

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ASIC Design Engineer - Pixel IP

At Apple - Sunnyvale

Posted on Oct 14

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ASIC Design Engineer - Pixel IP

At Apple - Sunnyvale

Posted on Oct 14

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At Apple - Waltham

Posted on Oct 12

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At Apple - Austin

Posted on Oct 11

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Design Verification Engineer

At Apple - Austin

Posted on Oct 11

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Design Verification Engineer

At Apple - Austin

Posted on Oct 11

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SoC Full Chip DV Engineer

At Apple - Austin

Posted on Oct 11

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SoC Full Chip DV Engineer

At Apple - Austin

Posted on Oct 11

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IP Integration Engineer

At Apple - San Francisco Bay Area

Posted on Oct 9

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Senior Principal Design Engineer

At Cadence Design Systems - Nanjing

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NoC Design Engineer, Multimedia Lab

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Lead Digital Verification Engineer

At Cadence Design Systems - Mount-royal

Posted on Nov 3

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Staff Engineer, Memory Layout Design

At Ansys - Noida

Posted on Oct 30

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PMU Analog Layout Engineer (m/f/d)

At Apple - Munich

Posted on Oct 19

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CPU Physical Electrical Analysis Engineer

At Apple - Santa Clara

Posted on Oct 19

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STA Engineer

At Apple - Austin

Posted on Oct 19

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Apple

Wireless SOC Verification Engineer

Irvine, CA$122,700 – $214,300Posted 24 days ago

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Why you should apply for a job to Apple:

Ranked as one of the Best Technology Companies in 2020
3.7/5 in overall job satisfaction
3.1/5 in supportive management
66% say women are treated fairly and equally to men
65% would recommend this company to other women
66% say the CEO supports gender diversity

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"Be the change you want to see in the world." The brand new, Apple designed Wireless/Bluetooth chips are at the heart of Networking in the newest iPhones. As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world!

Description

You will learn all aspects of a large-scale SOC, different types of SOC architectures, high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.","responsibilities":"Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes

Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF simulations

Create coverage driven verification plans from specifications, review and refine to achieve coverage targets

Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level

Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design

Work closely with DV methodology architects to improve verification metrics

Preferred Qualifications

Expertise in SystemVerilog coding and UVM methodology

Dedicated/hands-on ASIC & SOC DV experience

Experience with Formal Verification

Low Power Verification experience

Minimum Qualifications

Minimum requirement of a bachelor's degree

Experience with System Verilog, Verilog or UVM

Strong problem solving and analytical skills

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $122,700 and $214,300, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

About Apple

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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