SoC Physical Design Verification Engineer (M, F, D)
21 days ago Munich, Germany
About us
Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
- Size: 10,000+ employees
- Industry: Technology: Manufacturing
Why you should apply for a job to Apple:
Ranked as one of the Best Technology Companies in 2020
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3.1/5 in supportive management
66% say women are treated fairly and equally to men
65% would recommend this company to other women
66% say the CEO supports gender diversity
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Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. In this highly visible role, you will be a critical part of a growing team responsible for physical verification of SOC's in Munich, Germany.
Join us!
Description
Work with Physical Design team to understand chip architecture and drive physical verification aspects early in design cycle.","responsibilities":"Work on full chip DRC and LVS (including understanding of the PNR tools, ERC, high voltage check);
Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and supervise progress while offering physical verification support;
Support partition owners with Physical Verification activities, set goals, plan short and long-term work;
Resolve design and flow issues related to physical design, identify potential solutions and drive execution;
Collaborate with the package and floor-plan teams.
Preferred Qualifications
Familiar with hierarchical design approach, top-down design.
Experience with padring, bump, RDL design.
Familiar with GDS assembly, GDS requirements for hard macros.
Analog/Digital Layout design background and experience is a plus.
Experienced in industry standard tools used for physical verification such as Mentor Calibre as well as collaborating with foundries.
Familiar with TCL scripting.
Minimum Qualifications
Graduate in MSEE.
Ability to fluently speak and write in English.
Join us!
Description
Work with Physical Design team to understand chip architecture and drive physical verification aspects early in design cycle.","responsibilities":"Work on full chip DRC and LVS (including understanding of the PNR tools, ERC, high voltage check);
Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and supervise progress while offering physical verification support;
Support partition owners with Physical Verification activities, set goals, plan short and long-term work;
Resolve design and flow issues related to physical design, identify potential solutions and drive execution;
Collaborate with the package and floor-plan teams.
Preferred Qualifications
Familiar with hierarchical design approach, top-down design.
Experience with padring, bump, RDL design.
Familiar with GDS assembly, GDS requirements for hard macros.
Analog/Digital Layout design background and experience is a plus.
Experienced in industry standard tools used for physical verification such as Mentor Calibre as well as collaborating with foundries.
Familiar with TCL scripting.
Minimum Qualifications
Graduate in MSEE.
Ability to fluently speak and write in English.
Additional Information
- Posted: 21 days ago