320 jobs for "Integration Test Lead"

Software Development Engineer in Test, Retail and Marcom Engineering

At Apple - Sunnyvale

Posted on Oct 19

View job Apply on company site

Senior Director, Plant Manager - Missile Integration & Electronics

At Leidos - Huntsville

Posted on Nov 3

View job Apply on company site

Electro-Mechanical Technician

At Leidos - Huntsville

Posted on Nov 3

View job Apply on company site

System Integration Lead

At Apple - Austin

Posted on Oct 19

View job Apply on company site

Senior System Engineer

At Leidos - Remote / Flexible

Posted on Nov 2

View job Apply on company site

Power System Design and Integration Engineer

At Apple - San Francisco Bay Area

Posted on Oct 19

View job Apply on company site

Senior Software Integration Engineer - Assistant Vice President

At iCapital - Colorado Springs

Posted on Nov 4

View job Apply on company site

Access Management- Engineering- Senior Associate

At Fannie Mae - Remote / Flexible

Posted on Aug 30

View job Apply on company site

Product Engineer

At Cummins - Galesburg

Posted on Sep 3

View job Apply on company site

Software Engineer II: Innovus R&D

At Cadence Design Systems - Belo Horizonte

Posted on Sep 16

View job Apply on company site

Full-Stack Engineer 4 (Automation Quality Engineer)

At Capital One - Riverwoods · Richmond

Posted on Sep 24

View job Apply on company site

Manager, Office of Transformation Experience Design

At Mastercard - Harrison

Posted on Oct 2

View job Apply on company site

Bilingual (Spanish) - Product Delivery Manager - International Markets (LATAM) - (Remote-Eligible)

At Capital One - Remote / Flexible

Posted on Aug 29

View job Apply on company site

Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 27

View job Apply on company site

Manager, Office of Transformation Experience Design

At Mastercard - New York

Posted on Oct 2

View job Apply on company site

Director, System Engineering & Integration

At Cadence Design Systems - San Jose

Posted on Aug 9

View job Apply on company site

Manager, Office of Transformation Experience Design

At Mastercard - O'Fallon

Posted on Oct 2

View job Apply on company site

Legal Operations Coordinator

At Aristocrat - Las Vegas

Posted on Oct 9

View job Apply on company site

Manager, Quality Engineering

At Appian - McLean

Posted on Sep 29

View job Apply on company site

Quality Assurance Technical Lead

At iCapital

Posted on Oct 9

View job Apply on company site

Cadence Design Systems

Lead Design Engineer

Hyderabad, IndiaPosted Aug 27, 2026

Apply on company site View full job

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Profile

Role Title
Lead Design Engineer, SoC / Subsystem / IP Design

Experience
4to 18 years

Qualification:BE/BTECH/ME/MTECH

Role Summary
Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets.

Key Responsibilities

Own end-to-end RTL design and development of SoC, subsystem, and IP blocks. Translate architecture and product requirements into detailed micro-architecture and implementation plans. Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability. Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic. Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues. Work closely with verification teams to review test plans, support debug, and ensure design quality and closure. Collaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints. Support DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues. Review specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality. Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases. Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology. Contribute to design methodology improvements, reusable IP development, and automation initiatives.

Required Skills and Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field. 10 to 14 years of experience in digital design with strong exposure to IP, subsystem, and SoC development. Strong expertise in RTL design using Verilog/SystemVerilog. Solid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design. Strong experience in micro-architecture definition and hardware implementation. Good understanding of AMBA protocols such as AXI, AHB, and APB. Experience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges. Strong debugging skills for simulation, synthesis, and integration issues. Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows. Exposure to power, performance, and area optimization techniques. Scripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements. Strong communication and cross-functional collaboration skills.

Preferred Skills

Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs. Exposure to low-power design methodologies including UPF/CPF. Experience with formal verification support and silicon debug. Experience leading small design teams or owning major subsystems in large SoC programs.

Key Competencies

RTL and micro-architecture ownership SoC and subsystem integration Technical leadership Problem solving and debug Quality and design closure focus

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

View company profile