718 jobs for "Lead Test Engineer"

iPhone Touch Sensing Electrical Design Engineer

At Apple - San Francisco Bay Area

Posted on Oct 17

View job Apply on company site

Display Module Engineer

At Apple - Cupertino

Posted on Oct 17

View job Apply on company site

Software Development Engineer in Test - Video Codec

At Apple - Cupertino

Posted on Oct 17

View job Apply on company site

Principal Solid Propulsion Development Engineer - Hypersonics

At Leidos - Huntsville

Posted on Oct 7

View job Apply on company site

Senior Solid Propulsion Development Engineer - Hypersonics

At Leidos - Huntsville

Posted on Oct 7

View job Apply on company site

Lead Software Engineer

At Leidos - Albuquerque

Posted on Oct 2

View job Apply on company site

Lead Solutions Engineer, EUI

At TikTok - London

Posted on May 28

View job Apply on company site

Senior Software Engineer (MCP & RAG)

At Mastercard - Ashbourne

Posted on Jun 15

View job Apply on company site

Lead Digital Verification Engineer

At Cadence Design Systems - Montreal

Posted on Aug 28

View job Apply on company site

Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 27

View job Apply on company site

Senior Software Engineer (MCP & RAG)

At Mastercard - Tallaght

Posted on Jun 15

View job Apply on company site

Lead Design Engineer - Verification

At Cadence Design Systems - Shanghai

Posted on Jul 23

View job Apply on company site

Senior Software Engineer (MCP & RAG)

At Mastercard - Swords

Posted on Jun 15

View job Apply on company site

Quality Engineer - Electrical

At Aristocrat - Las Vegas

Posted on Oct 9

View job Apply on company site

Manager, Quality Engineering

At Appian - McLean

Posted on Sep 29

View job Apply on company site

Senior Design Engineer – Data Center Cooling

At Mitsubishi Electric Power Products - Freedom

Posted on Aug 19

View job Apply on company site

Quality Assurance Technical Lead

At iCapital

Posted on Oct 9

View job Apply on company site

Sr Staff Package Design Engineer

At Ansys - Nepean

Posted on Oct 9

View job Apply on company site

Principal Product Engineer - Imagery & Remote Sensing

At Esri - Redlands

Posted on Aug 25

View job Apply on company site

EMC Engineer

At Aristocrat - Las Vegas

Posted on Oct 9

View job Apply on company site

Cadence Design Systems

Lead Design Engineer

Hyderabad, IndiaPosted Aug 27, 2026

Apply on company site View full job

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Profile

Role Title
Lead Design Engineer, SoC / Subsystem / IP Design

Experience
4to 18 years

Qualification:BE/BTECH/ME/MTECH

Role Summary
Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets.

Key Responsibilities

Own end-to-end RTL design and development of SoC, subsystem, and IP blocks. Translate architecture and product requirements into detailed micro-architecture and implementation plans. Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability. Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic. Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues. Work closely with verification teams to review test plans, support debug, and ensure design quality and closure. Collaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints. Support DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues. Review specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality. Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases. Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology. Contribute to design methodology improvements, reusable IP development, and automation initiatives.

Required Skills and Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field. 10 to 14 years of experience in digital design with strong exposure to IP, subsystem, and SoC development. Strong expertise in RTL design using Verilog/SystemVerilog. Solid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design. Strong experience in micro-architecture definition and hardware implementation. Good understanding of AMBA protocols such as AXI, AHB, and APB. Experience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges. Strong debugging skills for simulation, synthesis, and integration issues. Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows. Exposure to power, performance, and area optimization techniques. Scripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements. Strong communication and cross-functional collaboration skills.

Preferred Skills

Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs. Exposure to low-power design methodologies including UPF/CPF. Experience with formal verification support and silicon debug. Experience leading small design teams or owning major subsystems in large SoC programs.

Key Competencies

RTL and micro-architecture ownership SoC and subsystem integration Technical leadership Problem solving and debug Quality and design closure focus

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

View company profile