187 jobs for "Formal Verification Engineer"

ASIC Design Engineer - Pixel IP DMA

At Apple - Cupertino

Posted on Oct 19

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Principal Software Engineer

At Cadence Design Systems - Noida

Posted on Sep 16

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CPU Design Verification Engineer

At Apple - Beaverton

Posted on Oct 19

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SOC Design Verification Engineer

At Apple - Irvine

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Lead Product Engineer

At Cadence Design Systems - Bangalore

Posted on Sep 16

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Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Aug 9

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SOC Design Verification Engineer

At Apple - Irvine

Posted on Oct 19

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Jul 23

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SOC Design Verification Engineer

At Apple - Irvine

Posted on Oct 19

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Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jul 12

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SOC Design Verification Engineer

At Apple - Irvine

Posted on Oct 19

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Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Jun 23

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SOC Design Verification Engineer

At Apple - Irvine

Posted on Oct 19

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Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Jun 18

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CPU Microarchitect/RTL Engineer

At Apple - Santa Clara

Posted on Oct 17

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Principal Application Engineer

At Cadence Design Systems - Shanghai

Posted on Dec 8

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CPU Clock Implementation Engineer

At Apple - Santa Clara

Posted on Oct 17

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CPU Processor Power Management Verification Engineer

At Apple - Santa Clara

Posted on Oct 17

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Sr Principal Design Engineer

At Cadence Design Systems - Bangalore

Posted on Sep 3

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CPU Processor Power Management Verification Engineer

At Apple - Santa Clara

Posted on Oct 17

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Cadence Design Systems

Principal Application Engineer

Shanghai, ChinaPosted Dec 8, 2025

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Why you should apply for a job to Cadence Design Systems:

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
The candidate will work closely with RTL design team to ensure successful tapeouts.

Requirement:

BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
Able to assume responsibility for a variety of technical tasks and to work independently
Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
Self-motivated, able to work as a team player, and good English communication skills

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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