701 jobs for "Test & Validation Engineer"

Ingenieur Application departement Marin Cummins Saint - Herblain

At Cummins - Remote / Flexible

Posted on Nov 3

View job Apply on company site

Analytical Structural and Dynamic Systems Tech Specialist

At Cummins - Darlington

Posted on Oct 24

View job Apply on company site

Software Engineer II (Preprocessing)

At Cadence Design Systems - Remote / Flexible

Posted on Oct 16

View job Apply on company site

Placement Student - AI, Digital & Zero Fuel Burn Testing

At Cummins - Daventry

Posted on Oct 1

View job Apply on company site

Placement Student - Product Design Engineer

At Cummins - Darlington

Posted on Oct 1

View job Apply on company site

Manager, Quality Engineering

At Appian - McLean

Posted on Sep 29

View job Apply on company site

Design Verification Engineer

At Apple - Remote / Flexible

Posted on Oct 3

View job Apply on company site

Principal Software Engineer

At Cadence Design Systems - Noida

Posted on Sep 16

View job Apply on company site

Software Engineer Expert

At Leidos - Chantilly

Posted on Aug 12

View job Apply on company site

Lead Aerospace Modeling and Simulation Engineer

At Leidos - Charlottesville

Posted on Oct 10

View job Apply on company site

Wireless Silicon Validation Engineer

At Apple - Waltham

Posted on Oct 19

View job Apply on company site

Battery Test Engineer

At Apple

Posted on Oct 17

View job Apply on company site

Electrical Engineer - Test and Instrumentation

At Apple - Cupertino

Posted on Oct 17

View job Apply on company site

Test Engineer (Packaging Design)

At Apple

Posted on Oct 15

View job Apply on company site

Test Engineer (Packaging Design)

At Apple

Posted on Oct 12

View job Apply on company site

Battery Test Engineer

At Apple

Posted on Oct 12

View job Apply on company site

AMS Lab Validation Engineer (m/f/d)

At Apple - München

Posted on Oct 7

View job Apply on company site

Lead Product Validation Engineer

At Cadence Design Systems - Zhubei

Posted on Oct 1

View job Apply on company site

Sr Principal Product Validation Engineer

At Cadence Design Systems - Beijing

Posted on Apr 1

View job Apply on company site

Lead Product Validation Engineer

At Cadence Design Systems - Shanghai

Posted on Nov 6

View job Apply on company site

Cadence Design Systems

Principal Software Engineer

Noida, IndiaPosted Sep 16, 2026

Apply on company site View full job

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment
Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution.
Defining verification strategy from IP to top digital integration
Define requirements for block level and full-chip level verification infrastructure
Create test plans for unit-level and chip-level verification and post-silicon validation
Debug failures and drive in-time resolution of bugs
Create coverage monitors and drive coverage to required quality targets
Develop tools, test benches, and test suites (UVM, C++/C ) to execute test plans.
Write functional coverage, analyze both code and functional coverage, and close coverage gaps
Develop and use unit level test benches that use functional tests as well as constrained random stimulus.
When needed, define and develop formal verification environment

Skills

BS or MS in EE, CS or related engineering discipline
5-10 years of demonstrated experience in verification of IPs, Digital Design and SoCs
Strong experience in design and verification standards and methodologies (SVA, UVM/OVM).
In-depth knowledge of Verilog and System Verilog HDL and experience with simulators and waveform debugging tools
Solid understanding and experience with verification of Digital Design and SoC architectures including test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
Strong experience creating test benches and automating regression test suites, preparing, and presenting detailed verification reviews
Knowledge of state-of-the-art EDA tools (e.g., Cadence Xcelium...)
Experience with formal verification is plus.
Programming experience in languages common to the industry (e.g., C, C++, Shell scripting)
Solid scripting skills (Python preferred or Perl or TCL).
Knowledge of test and DFT (Scan insertion, Scan compression, test coverage analysis, ATPG pattern generation, simulation and debug, IEEE 1149.1, 1500 and 1687 standards)

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

View company profile