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Cadence Design Systems

Senior Principal Software Engineer

San Jose$161,000 – $299,000Posted Sep 24, 2026

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Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.

We are looking for an experienced C/C++ software engineer to join the Xcelium Software Development Team to develop and enhance RTL/logic simulation products.

Responsibilities:

Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi-billion-node graphs.
Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
Collaborate with global team members to deliver high-quality results in a distributed environment.
Write Specifications and Unit Tests for your code.

Position Requirements/Qualifications:

MS/PhD in Computer Science or Electrical Engineering.
MS in Computer Science or Electrical Engineering with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
5+ years of experience in EDA software development.
Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool.
Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog.
Experience in multi-threaded/ concurrent programming.
Ability to quickly learn new technologies and adapt to project requirements.
Prior experience with RTL/logic simulation software development is an added plus.

The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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