253 jobs for "Lead Physical Design Engineer"

SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

View job Apply on company site

Lead Design Engineer

At Cadence Design Systems - Pune

Posted on Feb 19

View job Apply on company site

Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Sep 19

View job Apply on company site

SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

View job Apply on company site

Lead Design Engineer

At Cadence Design Systems - Hyderabad

Posted on Apr 10

View job Apply on company site

Lead Design Engineer

At Cadence Design Systems - Bangalore

Posted on Dec 18

View job Apply on company site

Senior DevOps Engineer

At Leidos - Bethesda

Posted on Nov 5

View job Apply on company site

CPU Implementation Lead Engineer

At Apple - Santa Clara

Posted on Oct 19

View job Apply on company site

Analytical Structural and Dynamic Systems Tech Specialist

At Cummins - Darlington

Posted on Oct 24

View job Apply on company site

Lead Substation Engineer - Technical Project Lead

At Leidos - Remote / Flexible

Posted on Oct 24

View job Apply on company site

Lead Substation Physical Engineer

At Leidos - Remote / Flexible

Posted on Oct 2

View job Apply on company site

NIKE, Inc. AI & Machine Learning, Innovation Graduate Internship

At Nike - Beaverton

Posted on Sep 30

View job Apply on company site

Program Manager for Academic Network

At Cadence Design Systems - Austin

Posted on Oct 21

View job Apply on company site

GPU Physical Design Engineer

At Apple - Austin

Posted on Oct 19

View job Apply on company site

Physical Design Lead - Custom Silicon Management

At Apple - Austin

Posted on Oct 19

View job Apply on company site

Product Manager, Apple Gift Card

At Apple - Cupertino

Posted on Oct 19

View job Apply on company site

FE integration & STA IP Lead- Advanced Technologies Group

At Apple - Haifa

Posted on Oct 16

View job Apply on company site

IC Package Design Engineer

At Apple - Austin Metro Area

Posted on Oct 15

View job Apply on company site

CPU MicroArchitect / RTL Engineer - Site Lead

At Apple - Beaverton

Posted on Oct 9

View job Apply on company site

Group Director, Design Engineering - Front End

At Cadence Design Systems - Austin

Posted on Oct 6

View job Apply on company site

Cadence Design Systems

Lead Design Engineer

Hyderabad, IndiaPosted Apr 10, 2024

Apply on company site View full job

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description:

To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout.
Responsible for physical verification methodology, including installation, development, qualification, automation, and support -
- To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows.
- And to support layout teams in verification flow issues.
Ensuring QA of the integrated PDK's with the custom design environment
- Add sub scripts to improve efficiency on QA process with adequate coverage.
General tool usage support - real-time support of all tools, creating bug workarounds and filing CCRs with R&D
Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks.
Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs.
Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment.

Position Requirements:

Bachelor's Degree in Electrical/Electronic Engineering or equivalent .
4-7 years of Work experience in PDK development and CAD enablement.
Expertise in Cadence Python, SKILL, Perl programming languages.
Knowledge of deep sub-micron CMOS processes, device physics and layout design.
Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting.
Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus.
Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc)
Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus
Excellent technical problem solving skills.
Excellent communication and presentation skills.

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

View company profile