11 jobs for "High Speed PHY FW Engineer"

Intern - Design Engineering

At Cadence Design Systems - Shanghai

Posted on Nov 5

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Lead Design Engineer

At Cadence Design Systems - Seoul

Posted on Nov 3

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Sr Design Engineer

At Cadence Design Systems - Seoul

Posted on Nov 3

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Accounts Receivable and Collections Representative

At Esri - Redlands

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General Laborer 1

At Altria Group, Inc. - Hopkinsville

Posted on Nov 4

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Client Partner, Peru (Ad-Sales) - Bogota - GBS

At TikTok - Bogotá

Posted on Nov 5

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Director, Software Engineering

At Mastercard - Arlington

Posted on Nov 3

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Care Coordinator Supervisor - DoD Healthcare (GNAL-NG)

At Leidos - Remote / Flexible

Posted on Nov 7

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Client Partner, Ecuador - Global Business Solutions - GBS

At TikTok - Bogotá

Posted on Nov 5

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Benefits Operations Administrator

At Alight Solutions - Noida

Posted on Nov 4

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Account Executive - Insurance

At Appian - London

Posted on Nov 4

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Cadence Design Systems

Intern - Design Engineering

Shanghai, ChinaPosted 4 days ago

Apply on company site View full job

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Technology Companies in 2024
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the team:
Our team deliver many high-performance products based on the industry's advanced technology with high frequencies up to 6400MHz. Our product processes include TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Focus on high speed digital DDR and HBM/UCIe/PCIe/eUSB IPs physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.

实习 - 数字后端工程师 (工作地点:上海)

职位描述:
(1)芯片物理设计, 后端布局布线，STA，物理验证等。
(2)团队合作，负责电路后端设计及交付，设计质量和进度控制

职位需求:
(1)微电子,电子工程硕士以上学历
(2)较强的问题分析以及团队合作能力
(3)较强的中英文口语沟通及写作能力
(4)熟悉数字后端工具
(5)积极主动, 有责任心

**每周可以工作至少3天，实习期6-8个月

We're doing work that matters. Help us solve what others can't.

About Cadence Design Systems

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology: Manufacturing

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