SoC Physical Design Engineer, STA/Timing
21 days ago Beaverton, OR
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Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product.
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.
Description
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
- Work with the Physical Design team, highlighting issues and best practices.
- Help create timing ECO's for project tapeout.
- Create and maintain scripts and methodologies for analysis and runs.
- Create documentation and help with guidelines/specs.
- Deep analysis of timing paths to identify key issues.
- Implement timing infrastructure.
Preferred Qualifications
Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
Experience with STA and methodologies for timing closure.
Familiar with circuit modeling, including SPICE models, and/pr worst-case corner selection.
Good programming skills with Perl and TCL.
Experience with large design STA and Timing Closure.
Familiar with ECO techniques and implementation.
Good communicator who can accurately describe issues and follow them through to completion.
Minimum Qualifications
Minimum Bachelor's degree with 0+ years of experience
Experience with STA.
Experience with noise, crosstalk, and/or OCV effects.
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.
Description
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
- Work with the Physical Design team, highlighting issues and best practices.
- Help create timing ECO's for project tapeout.
- Create and maintain scripts and methodologies for analysis and runs.
- Create documentation and help with guidelines/specs.
- Deep analysis of timing paths to identify key issues.
- Implement timing infrastructure.
Preferred Qualifications
Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
Experience with STA and methodologies for timing closure.
Familiar with circuit modeling, including SPICE models, and/pr worst-case corner selection.
Good programming skills with Perl and TCL.
Experience with large design STA and Timing Closure.
Familiar with ECO techniques and implementation.
Good communicator who can accurately describe issues and follow them through to completion.
Minimum Qualifications
Minimum Bachelor's degree with 0+ years of experience
Experience with STA.
Experience with noise, crosstalk, and/or OCV effects.
Additional Information
- Posted: 21 days ago