Senior SoC Digital Design Engineer, Multimedia Lab
Apr 2, 2026 San Jose
About us
TikTok is the leading destination for short-form mobile video and our mission is to inspire creativity and bring joy.
- Size: 10,000+ employees
- Industry: Technology: Consumer Internet
Why you should apply for a job to TikTok:
4.5/5 in overall job satisfaction
4.5/5 in supportive management
100% say women are treated fairly and equally to men
100% would recommend this company to other women
100% say the CEO supports gender diversity
Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›
Responsibilities
About the team:
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities
- Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
- RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
- Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
- Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
- Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.
Qualifications
Minimum Qualifications:
- Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
- 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
- Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
- Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
- Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.
Preferred Qualifications:
- Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
- Proven experience in SoC-level performance profiling and bottleneck analysis.
- Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
- Successful tape-out experience in advanced process nodes (7nm/5nm/3nm)
Job Information
[For Pay Transparency] Compensation Description (annually)
The base salary range for this position in the selected city is $218400 - $480000 annually.
Compensation may vary outside of this range depending on a number of factors, including a candidate's qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.
Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure).
The Company reserves the right to modify or change these benefits programs at any time, with or without notice.
For Los Angeles County (unincorporated) Candidates:
Qualified applicants with arrest or conviction records will be considered for employment in accordance with all federal, state, and local laws including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Our company believes that criminal history may have a direct, adverse and negative relationship on the following job duties, potentially resulting in the withdrawal of the conditional offer of employment:
1. Interacting and occasionally having unsupervised contact with internal/external clients and/or colleagues;
2. Appropriately handling and managing confidential information including proprietary and trade secret information and access to information technology systems; and
3. Exercising sound judgment.
About the team:
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities
- Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
- RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
- Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
- Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
- Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.
Minimum Qualifications:
- Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
- 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
- Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
- Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
- Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.
Preferred Qualifications:
- Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
- Proven experience in SoC-level performance profiling and bottleneck analysis.
- Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
- Successful tape-out experience in advanced process nodes (7nm/5nm/3nm)
About the team:
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities
- Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
- RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
- Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
- Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
- Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.
Qualifications
Minimum Qualifications:
- Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
- 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
- Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
- Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
- Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.
Preferred Qualifications:
- Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
- Proven experience in SoC-level performance profiling and bottleneck analysis.
- Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
- Successful tape-out experience in advanced process nodes (7nm/5nm/3nm)
Job Information
[For Pay Transparency] Compensation Description (annually)
The base salary range for this position in the selected city is $218400 - $480000 annually.
Compensation may vary outside of this range depending on a number of factors, including a candidate's qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.
Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure).
The Company reserves the right to modify or change these benefits programs at any time, with or without notice.
For Los Angeles County (unincorporated) Candidates:
Qualified applicants with arrest or conviction records will be considered for employment in accordance with all federal, state, and local laws including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Our company believes that criminal history may have a direct, adverse and negative relationship on the following job duties, potentially resulting in the withdrawal of the conditional offer of employment:
1. Interacting and occasionally having unsupervised contact with internal/external clients and/or colleagues;
2. Appropriately handling and managing confidential information including proprietary and trade secret information and access to information technology systems; and
3. Exercising sound judgment.
Responsibilities
ResponsibilitiesAbout the team:
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities
- Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
- RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
- Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
- Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
- Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.
Qualifications
QualificationsMinimum Qualifications:
- Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
- 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
- Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
- Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
- Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.
Preferred Qualifications:
- Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
- Proven experience in SoC-level performance profiling and bottleneck analysis.
- Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
- Successful tape-out experience in advanced process nodes (7nm/5nm/3nm)
Additional Information
- Salary: $218,400 – $480,000
- Posted: Apr 2, 2026